Question

Draw logic diagram of 4:1 multiplexer & give its truth table.

Answer 1

### Logic Diagram of a 4:1 Multiplexer

A 4:1 multiplexer (MUX) selects one of four input signals and forwards the selected input to a single output line based on the values of two select lines. Here's how to represent it:

```
         +-----+
    S1 --|     |
         |  4:1|--- Y (Output)
    S0 --| MUX |
         |     |
    A0 --|     |
    A1 --|     |
    A2 --|     |
    A3 --|     |
         +-----+
```

### Components

- **Inputs:** A0, A1, A2, A3
- **Select Lines:** S0, S1
- **Output:** Y

### Truth Table

The truth table for a 4:1 multiplexer is as follows:

| S1 | S0 | Output Y | Selected Input |
|----|----|----------|-----------------|
| 0  | 0  |   A0     | A0              |
| 0  | 1  |   A1     | A1              |
| 1  | 0  |   A2     | A2              |
| 1  | 1  |   A3     | A3              |

### Explanation

- The **select lines** (S0 and S1) determine which of the four inputs (A0 to A3) is connected to the output Y.
- When both select lines are low (0, 0), the output is A0.
- When S0 is high and S1 is low (0, 1), the output is A1.
- When S0 is low and S1 is high (1, 0), the output is A2.
- When both select lines are high (1, 1), the output is A3.

This configuration allows for selecting one of the four input signals based on the binary value represented by the select lines.

Answer 2

A 4:1 multiplexer (4-to-1 MUX) is a digital device that selects one of four input data lines and forwards the selected input to a single output line. The selection of the input is controlled by two select lines.

### Logic Diagram of a 4:1 Multiplexer

Here is the logic diagram of a 4:1 multiplexer:

```
        S1     S0
         |      |
        --------------
        |            |          
    ----| AND |      |       ----
    |   --------------       |     |
  D0|   --------------       |MUX  |    OUT
    |---| AND | S1' |      ----|    |---
        --------------         |   |
                                |   |
    ----        --------------  |  |
    |   |S1'   |  AND | S0'   |  |
  D1|---        --------------      |  
    |         --------------        |
    ----| AND | S1 | S0'        |  
        --------------           |
                                  |
  D2|------- | AND | S1'|S0        |
   |         --------------
   
D3|--------| AND | S1 S0      |   
   |        --------------     
```

### Explanation of the Logic Diagram:

1. **Inputs:**
   - **D0, D1, D2, D3**: Data inputs.
   - **S0, S1**: Selection lines.

2. **AND Gates**:
   - Each AND gate combines one data input with the appropriate select lines.
   - The output of an AND gate is high only when both the data input and the select lines' conditions are met.

3. **OR Gate**:
   - The outputs of all the AND gates are fed into a single OR gate.
   - The OR gate outputs a high signal when any of its inputs are high, which corresponds to the selected input data line.

### Truth Table of 4:1 Multiplexer

The truth table of a 4:1 multiplexer is as follows:

| **S1** | **S0** | **Output (Y)** |
|:------:|:------:|:--------------:|
|   0    |   0    |       D0       |
|   0    |   1    |       D1       |
|   1    |   0    |       D2       |
|   1    |   1    |       D3       |

### Explanation of the Truth Table:
- **S1 S0 = 00**: The multiplexer selects **D0** and outputs its value.
- **S1 S0 = 01**: The multiplexer selects **D1** and outputs its value.
- **S1 S0 = 10**: The multiplexer selects **D2** and outputs its value.
- **S1 S0 = 11**: The multiplexer selects **D3** and outputs its value.

### Summary
The 4:1 MUX selects one of the four inputs based on the values of the select lines and forwards the selected input to the output. The logic diagram uses AND gates to combine the inputs with the selection lines and an OR gate to consolidate the outputs from the AND gates.