A **half adder** is a fundamental digital circuit used in binary addition. It adds two single-bit binary numbers and produces two outputs: a **sum** and a **carry**. It’s called a "half" adder because it doesn’t account for a carry input from a previous addition (which is the role of a full adder).
### Truth Table for Half Adder
| Input A | Input B | Sum (S) | Carry (C) |
|---------|---------|---------|-----------|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
### Explanation of Outputs:
- **Sum (S)**: The sum bit is the result of the addition of inputs A and B. This can be obtained using an XOR (exclusive OR) gate:
\[
\text{Sum} (S) = A \oplus B
\]
This means the sum is `1` when only one of the inputs is `1` (i.e., A=0, B=1 or A=1, B=0), and it’s `0` when both inputs are either `0` or `1`.
- **Carry (C)**: The carry bit is the overflow bit that represents the sum exceeding the value `1`. This is produced when both inputs are `1` (1+1 = 10, so the carry is `1`). It can be calculated using an AND gate:
\[
\text{Carry} (C) = A \cdot B
\]
The carry is `1` only when both inputs are `1`, and `0` otherwise.
### Logic Diagram:
- The sum output (S) is connected to an XOR gate.
- The carry output (C) is connected to an AND gate.
### Applications of Half Adder:
- It forms the building block for more complex arithmetic circuits like **full adders**, which can handle carry inputs.
- Used in digital circuits where simple binary addition is required, such as in **ALUs (Arithmetic Logic Units)** and **binary counters**.
### Limitations of a Half Adder:
- It cannot take into account a carry input from a previous stage of addition. This is why, in more complex addition tasks, multiple half adders are combined with **full adders**, which can handle carry inputs.
To summarize, a half adder is the simplest form of a binary adder circuit, and its simplicity makes it a useful tool in many digital systems, especially where basic binary addition is needed.